FPGA: FPGA: Heartbeat
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FPGA: Heartbeat, My First Verilog Program My Dad and I wanted to learn more about Verilog. We had torn into a PS2 mouse decode algorithm and wound up hopelessly lost. The code acted erratically (undoubtedly our fault). We drank a beer or two and decided a new tact was necessary. My idea was to write some code and put an emphasis on looking at the RTL Schematic for things we build. I highly recommend that course of action for anybody interested in either Verilog or VHDL. Look at the schematic built from your source code. It's important that you understand it. With that methodology, we wrote a heartbeat module in Verilog:
	always @(posedge clock_in)
	   begin : Heartbeat_hotel
	      if (reset) begin
	         count <= 0;
		 clock_out <= 0;
	      end else if (count == `K) begin
	         count <= 0;
		 clock_out <= ~clock_out;
	      end else
	         count <= count + 1;
	   end // Heartbeat_hotel
You can download the the complete heartbeat.v file here Here is a test program to drive the heartbeat.
module test_hb(clock, reset_n, led);
	input clock;
	input reset_n;
	output led;

	heartbeat #(25, 1_000_000) 
		one_sec_blink (clock, ~reset_n, led);

And, for a Burch B5-X300, here is a .ucf file:
# These device are on the B5-X300 board.
NET "clock" LOC = "P77"; #  b5-clk
NET "reset_n" LOC = "P57"; #  b5-btn
NET "led" LOC = "P82"; #  b5-led